It used to be that designing hardware required schematics and designing software required code. Sure, a lot of people could jump back and forth, but it was clearly a different discipline. Today, a lot of substantial digital design occurs using a hardware description language (HDL) like Verilog or VHDL. These look like software, but as we’ve pointed out many times, it isn’t really the same. [Zipcpu] has a really clear blog post that explains how it is different and why.
[Zipcpu] notes something we’ve seen all too often on the web. Some neophytes will write sequential code using Verilog or VHDL as if it was a conventional programming language. Code like that may even simulate. However, the resulting hardware will — at best — be very inefficient and at worst will not even work.
We did mildly disagree with one statement in the post: “…no digital logic design can work without a clock.” However, [Zipcpu] goes on to elaborate and we agree with the elaboration. However, it is important to note that asynchronous and combinatorial logic don’t use a clock in the conventional sense of the word. Combinatorial logic — for example, a bunch of AND and OR gates — can only handle simple tasks and full-blown asynchronous design is tough and not likely to be something a new FPGA developer will encounter.
The reality is that nearly all significant digital design uses clocks is because it makes the design manageable. Essentially, the clock tells all parts of the circuit to start processing and sets a deadline for the various combinatorial parts to complete. Without the clock, you’d have to deal with the issue when, for example, an adder presents a result before the carry from another stage arrives to change that answer. With a clock, as long as the right answer is ready by the clock edge, you don’t care about exactly how long it takes.
This is especially important because Verilog and VHDL don’t execute line-by-line as a software developer would expect. Instead, HDL constructs become circuits and all the circuits operate at one time. This parallelism can be difficult to manage, but it is what makes FPGAs ideal for high-speed computations and fast response times.
The section of the post about how much logic to put between clocks is what you usually call “making timing.” The FPGA tools have a scary amount of data about how much time it takes for a signal to travel from one part of the FPGA to another. If the tool detects that the transit time between two clocked elements exceeds the clock period, it will flag that as an error. You can increase the clock speed or shorten the path either physically or logically.
Overall, this is an excellent introduction to a tough subject and has a lot of real-world advice in it. If you want to read our take on it, we did a multipart Verilog tutorial using the inexpensive Lattice iCEstick board. There’s also a practical example using the same board. The tutorial even had some videos, the first of which appears below.
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